Recently, there is a rapid increase in functionality of electrical apparatuses including portable information systems such as cellphone; computer and its peripheral devices; various home information appliances, and others. Along with the trend, there is also an increasing demand for improvement in density of the circuit on the circuit board used in these electrical apparatuses. For improvement in density of such a circuit, needed is a method of producing circuits having narrower line width and line interval accurately. There are problems, such as short circuiting and migration between wires, frequently found in high-density wiring circuit. In addition, narrow-width wiring leads to deterioration in mechanical strength of wiring, making the resulting circuits more vulnerable to circuit breakage, for example, by imp act.
Subtractive and additive methods have been known as the methods of forming such a circuit on circuit board. The subtractive method is a method of forming a circuit by removing (subtracting) the metal in the area on the surface of a metal clad laminate, excluding that where the circuit is desirably formed. On the other hand, the additive method is a method of forming a circuit only in the region on the insulative substrate where a circuit is desirably formed by electroless plating.
The subtractive method is a method of leaving a metal only in the circuit-forming region, by etching of the thick-film metal foil. The metal in the region removed is only wasted by the method. In contrast, the additive method, by which the electrolessly plated film is formed only in the region where the metal wires are desirably formed, does not result in waste of the metal. From the point above, the additive method is more preferable as the circuit-forming method.
Full-additive method, one of typical conventional additive methods, will be described with reference to the schematic cross-sectional views of FIGS. 1A to 1E.
As shown in FIG. 1A, a plating catalyst 102 is deposited on the surface of an insulative substrate 100 having throughholes 101. The surface of the insulative substrate 100 is previously roughened. As shown in FIG. 1B, a photoresist layer 103 is then formed thereon. Then as shown in FIG. 1C, the surface of the photoresist layer 103 is exposed to light via a photomask 110 having a particular patterned circuit. As shown in FIG. 1D, the circuit pattern is then developed. As shown in FIG. 1E, metal wires 104 are formed after electroless copper plating on the circuit pattern formed by development and on the internal wall surface of the throughholes 101. A circuit is formed on an insulative substrate 100 by these steps.
In the conventional additive method described above, a plating catalyst 102 is deposited on the entire surface of the insulative substrate 100. As a result, it caused the following problem. If the photoresist layer 103 is developed at high accuracy, a plated film can be formed only in the region unprotected with the photoresist. However, if the photoresist layer 103 is not developed at high accuracy, an undesirably plated region 105 may remain unremoved in the region where the plating is undesirable, as shown in FIG. 2. Such a trouble occurs, because the plating catalyst 102 is deposited on the entire surface of the insulative substrate 100. The undesirably plated region 105 causes short circuiting and migration between neighboring circuits. The short circuiting and the migration are found more frequently, when a circuit having narrower line width and line interval is formed.
JP-A No. 58-186994 (Patent Document 1) discloses the following method:
A protective film is first coated on an insulative substrate (first step). Then, grooves and throughholes corresponding to a wiring pattern are formed on the insulative substrate coated by the protective film by mechanical processing or irradiation of laser beam (second step). An activation layer is then formed on the entire surface of the insulative substrate (third step). The activation layer is then left only on the internal wall surface of the grooves and throughholes, by separating the protective film and thus removing the activation layer on the insulative substrate (fourth step). Then, an electrically conductive layer is formed selectively only on the internal wall surface of the activated grooves and throughholes by plating on the insulative substrate without use of a plating protective film (fifth step). The method will be described with reference to schematic cross-sectional views of FIGS. 3A to 3E explaining the steps of forming a metal wiring pattern.
As shown in FIG. 3A, a protective film 201 is coated on the surface of an insulative substrate 200. Then as shown in FIG. 3B, grooves 202 and throughholes 203 in a desired wiring pattern are formed on the insulative substrate 200 coated by the protective film 201. As shown in FIG. 3C, a plating catalyst 204 is then deposited on the surface of the grooves 202 and throughholes 203 and also on the surface of the protective film 201. As shown in FIG. 3D, the plating catalyst 204 is left only on the surface of the groove 202 and throughhole 203 after separation of the protective film 201. As shown in FIG. 3E, an electrolessly plated film is formed selectively only in the region having the residual plating catalyst 204, giving an electrically conductive layer 205 only on the internal wall surface of the throughholes 203 and grooves 202.
Patent Document 1 describes a method of coating and heat-curing a thermosetting resin on an insulative substrate as a protective film, machine-processing the protective film and the insulative substrate according to a particular wiring pattern, and removing the thermosetting resin on the insulative substrate surface with a solvent (Patent Document 1, p. 2, left bottom column, 1.16 to right bottom column, 1.11).
The kind of the thermosetting resin used as the protective film in Patent Document 1 is not described specifically. Common thermosetting resins are higher in solvent resistance and thus, had a problem that the resins are hardly removed simply with a solvent. Such a thermosetting resin is often excessively adhesive to the resinous substrate, making it difficult to separate only the protective film reliably without leaving fragments of the protective film on the resinous substrate surface. If a strong solvent is used for sufficient separation or the substrate is immersed in a solvent for a prolonged period of time, the plated catalyst on the substrate surface is removed together. In this case, no electrically conductive layer is formed in the region where the plating catalyst is removed. In addition, use of a strong solvent or immersion for a prolonged period of time occasionally resulted in fragmentation of the protective film of thermosetting resin and redispersion of the plating catalyst of protective film into the solvent. The plating catalyst redispersed in solvent is redeposited on the resin substrate surface, possibly forming an undesirably plated film in the region. For that reason, it was difficult to form a circuit having an accurate pattern by the method disclosed in Patent Document 1.
Alternatively, JP-A No. 57-134996 (Patent Document 2) discloses the following method as another additive method: A first photosensitive resin layer soluble in organic solvent and a second photosensitive resin layer soluble in alkali solution are first formed on an insulative substrate. The first and second photosensitive resin layers are exposed to light via a photomask in a particular circuit pattern. The first and second photosensitive resin layers are then developed. A catalyst was then deposited by adsorption on the entire surface having dents formed after development, and only the undesired catalyst is removed, while the alkali-soluble second photosensitive resin is dissolved with an alkaline solution. A circuit is then formed accurately only in the region having the plating catalyst. However, such a method demands preparation of two kinds of photosensitive resin layer different in solvent solubility, development thereof with two kinds of solvents, and solubilization of the second photosensitive resin with an alkaline solution after adsorption of catalyst, and thus, the production process was very complicated.
Preparation of an electrical circuit having narrow line width and line interval by using the circuit-forming method described above also caused the following problem: Specifically, decrease in line width and line interval of the circuit leads to deterioration in wire strength. The deterioration in wire strength in turn leads to deterioration in reliability of the resulting electronic devices.
Specifically, a problem that may occur in the circuit board, when used in portable information systems such as cellphones, will be described below as an example. Relatively large LSI (Large Scale Integration) circuit boards are used in portable information systems. Such LSIs are connected to the land regions formed on circuit board by solder bumping. Portable information systems are often exposed to impacts, while they are carried. Exposure to such an impact makes a physical force applied to the LSI mounted, possibly damaging the metal wires constituting the land regions by breakage. Similarly, the LSIs may also be damaged by separation of the contact points between the LSIs and the substrate. Decrease in line width and line interval of the electrical circuit leads to increase in frequency of circuit damage.
To solve the problems above, the metal wires may be reinforced by increase of the line width of the circuit wire. However, such a method prohibits increase in circuit density. The thickness of the metal wires in the circuit obtained by the subtractive method depends on the thickness of the copper foil used, and thus, it is also not possible to reinforce the metal wires by thickening the film.
Recently, a build-up method of forming each layer of circuit one by one and laminating the layers while forming interlayer-connecting vias therein is known as the method of producing a high-density multilayer circuit board. The general steps of the build-up method will be described with reference to the schematic cross-sectional vies of FIGS. 4A to 4G.
In the build-up method, as shown in FIG. 4A, metal wires 301 are first formed on a first-layer insulative substrate 300. Then as shown in FIG. 4B, an insulation resin layer 302 is formed on the surface of the insulative substrate 300. The insulation resin layer 302 is formed, for example, by coating and hardening a liquid resin or bonding an insulator film thereto. Then as shown in FIG. 4C, viaholes (IVH) 304 are formed in the insulation resin layer 302. IVHs 304 are formed by laser processing. As shown in FIG. 4D, a resinous residue smear (resin smear) 305 remains on the bottom of each IVH 304 formed by laser processing. The metal wire 301 is a thin film. Accordingly, the metal wire 301 may be thinned or may have a hole, if the resin smear 305 is treated for complete removal by laser processing. For that reason, the laser irradiation should be terminated before complete removal of the insulation resin.
The resin smear 305 remaining on the bottom of IVH 304 may possibly cause conductivity troubles. Thus as shown in FIG. 4D, the resin smear 305 should be removed. The resin smear 305 is removed by desmear treatment. The desmear treatment is a treatment of removing the resin smear by solubilization, specifically by dissolving the resin smear, for example, in permanganic acid solution. Then as shown in FIG. 4E, a photoresist layer 306 is formed on the surface of the insulation resin layer 302. As shown in FIG. 4F, the surface of the photoresist layer 306 is then exposed to light via a particular circuit-patterned photomask not shown in the Figure, and the resulting circuit pattern is developed. As shown in FIG. 4G, metal wires 307 are formed by electroless copper plating on the developed circuit patterned regions and throughholes.